The present invention relates generally to the construction of semiconductor integrated circuit devices and more particularly to systems for interconnecting devices in an integrated circuit.
As the device density in Very Large Scaled Integrated (VLSI) circuits increases, a number of problems concerning interconnect fabrication and functionality will be exacerbated. These trends not only require that the pitch of the metal, on any one level, is dramatically reduced but that the number of these tightly pitched metal levels increase. Design requirements of this nature will occur for high speed bipolar and MOS logic in mainframe computers and qate arrays with tens to hundreds of thousand of gates. Within the next decade, metal pitches approaching 2 microns will be commonplace with three to four levels of dense interconnect. Chips having an area of one square centimeter could potentially have tens to hundreds of meters of interconnect to effectively utilize all logic elements on the die.
To further complicate matters, the overall clock cycle of these circuits will eventually push well into the gigahertz range making these microwave integrated circuits. This will be especially true of state-of-the-art bipolar ECL devices. The wavelength of the signal propagating along the interconnects in many cases will approach the edge dimensions of the die making high speed interconnect coupling which is presently a problem on the printed circuit board level move on chip.
These requirements raise a number of interrelated problems. For example, the effective cross section of the interconnect will decrease unless the height to width ratios of the metal lines are increased. If the metal cross section is reduced without an equivalent fractional decrease in the current density or use of a physically more robust conductor, failure due to electromigration will become more probable. The thermal dissipation of energy generated by these larger devices during operation will also adversely affect the interconnect electromigration resistance. This will occur because the interconnects will be running at higher temperatures unless more efficient device cooling is employed. If the height of the interconnect is increased in tightly pitched structures, the capacitive and inductive coupling between adjacent interconnects in the same plane and planes above and below it also increases. These coupling effects lead to increased system noise and other spurious electrical effects which are detrimental to the performance of the integrated circuit.
In addition, as the speed of device operation increases, it will become necessary to match the overall circuit impedance with that of an external power source for optimal device efficiency with little reflected power. This will be especially true for VISI microwave circuits. A further problem will occur when the cross section of the interconnect is reduced. The resistance per unit length increases giving a large signal attenuation when the interconnect runs on chip are quite long (on the order of a centimeter).
In general, the ratio of inductance per unit length to capacitance per unit length will be more important from a designers viewpoint than the total inductance or capacitance alone. This ratio will effectively determine the characteristic impedance of the interconnect. Based on this situation, it is desirable to be able to "tune" the circuits for impedance mismatch caused by the L/C ratio obtained through design. This can be done for example by using stubs to match the circuit impedance with sources from the outside world. The attenuation and crosstalk issues, however, will continue to play a greater role in operational restrictions on very high speed circuits and must be addressed as a different issue.
In view of the above, it appears that it will be necessary to vertically increase the height/width ratio of the interconnect levels to maintain a low resistance and attenuation; effectively eliminate undesirable mutual coupling between the interconnects using a coaxial shielding approach; and match the device and source characteristic impedances by using stub tuning techniques on chip as a final fabrication step in the device processing.
Although the discussion has so far focused on the electrical requirements of the interconnect systems, it is important to appreciate other physical fabrication requirements. As devices and interconnect lines move closer together, mechanical flaws in the interconnect material can cause shorting between adjacent metal lines. This effect translates in device failure and a reduced die yield. Hillocking is one such mechanical flaw which can cause shorting. This phenomenon occurs due to thermally generated differential stresses between the interconnect and a support material which have substantially different thermal expansion coefficients. The flaw is manifested by random local deformation of conductor material in the form of bumps which protrude from the conductor surface. In some cases these bumps are large enough to short adjacent levels of wiring together resulting in the failure of a device. As the interconnect lines are moved closely together, such deformation is more likely to cause shorting of adjacent interconnect lines. This can become a severe problem especially when an encapsulating material, which can restrain this deformation, is not employed.
Consequently, there exists a need for an interconnect system wherein unwanted electrical coupling between interconnect lines can be minimized. Secondly, there exists a need to keep the resistance of the interconnect small by employing larger line cross sectional areas so attenuation losses are not appreciable and electromigration effects are avoided. In addition, it is desirable to find better ways to remove thermal energy from large high power devices during operation by using the interconnect, if possible. Finally, there exists a need for an interconnect system which, in addition to satisfying the above stated needs, also possesses superior mechanical strength at the required processing and device operational temperatures.